PDP83TG720SWCSTQ1 datasheet(129/199 Pages) TI

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7.6.2.71 PRBS_STATUS_6 Register (Address = 0x620) [reset = 0x0]

PRBS_STATUS_6 is shown in Table 7-94.

Return to the Summary Table.

Table 7-94. PRBS_STATUS_6 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

RESERVED

3b000

Reserved

pkt_done

1b0

Set when all MAC packets w CRC are transmitted

1b0 = MAC packet transmission in progress

1b1 = MAC packets transmission completed

pkt_gen_busy

1b0

1 = Packet generator is in process 0 = Packet generator is not in

process

1b0 = Packet generator is not in process

1b1 = Packet generator is in process

prbs_pkt_ov

1b0

If set, packet counter reached overflow Overflow is cleared when

PRBS counters are cleared - done by setting bit #1 of prbs_status_6

1b0 = No overflow

1b1 = Packet counter overflow

prbs_byte_ov

1b0

If set, bytes counter reached overflow Overflow is cleared when

PRBS counters are cleared - done by setting bit #1of prbs_status_6

1b0 = No overflow

1b1 = byte counter overflow

prbs_lock

1b0

1 = PRBS checker is locked sync) on received byte stream 0 =

PRBS checker is not locked

1b0 = PRBS checker is not locked

1b1 = PRBS checker is locked sync) on received byte stream

7-0

prbs_err_cnt

8b00000000 Holds number of errored bits received by the PRBS checker Value in

this register is locked when write is done to bit[0] or bit[1] When

PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing

bit 0 generates a lock signal for the PRBS counters. Writing bit 1

generates a lock and clear signal for the PRBS counters

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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