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LSM6DSV320X Datasheet(PDF) 151 Page - STMicroelectronics |
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LSM6DSV320X Datasheet(HTML) 151 Page - STMicroelectronics |
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151 / 212 page ![]() 13.43 SFLP_ODR (5Eh) Sensor fusion low-power output data rate configuration register (R/W) Table 363. SFLP_ODR register 0(1) 1(2) SFLP_GAME _ODR_2 SFLP_GAME _ODR_1 SFLP_GAME _ODR_0 0(1) 1(2) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 364. SFLP_ODR register description SFLP_GAME_ODR_[2:0] ODR configuration of the SFLP game algorithm: (000: 15 Hz; 001: 30 Hz; 010: 60 Hz; 011: 120 Hz (default); 100: 240 Hz; 101: 480 Hz) 13.44 FSM_ODR (5Fh) Finite state machine output data rate configuration register (R/W) Table 365. FSM_ODR register 0(1) 1(2) FSM_ODR_2 FSM_ODR_1 FSM_ODR_0 0(1) 1(2) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 366. FSM_ODR register description FSM_ODR_[2:0] Finite state machine ODR configuration: (000: 15 Hz; 001: 30 Hz (default); 010: 60 Hz; 011: 120 Hz; 100: 240 Hz; 101: 480 Hz; 110: 960 Hz) LSM6DSV320X Embedded functions register description DS14623 - Rev 1 page 151/212 |
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