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LSM6DSV320X Datasheet(PDF) 152 Page - STMicroelectronics |
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LSM6DSV320X Datasheet(HTML) 152 Page - STMicroelectronics |
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152 / 212 page ![]() 13.45 MLC_ODR (60h) Machine learning core output data rate configuration register (R/W) Table 367. MLC_ODR register 0(1) MLC_ODR_2 MLC_ODR_1 MLC_ODR_0 0(1) 1(2) 0(1) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 368. MLC_ODR register description MLC_ODR_[2:0] Machine learning core ODR configuration: (000: 15 Hz; 001: 30 Hz (default); 010: 60 Hz; 011: 120 Hz; 100: 240 Hz; 101: 480 Hz; 110: 960 Hz) 13.46 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) Step counter output register (R) Table 369. STEP_COUNTER_L register STEP_7 STEP_6 STEP_5 STEP_4 STEP_3 STEP_2 STEP_1 STEP_0 Table 370. STEP_COUNTER_L register description STEP_[7:0] Step counter output (LSbyte) Table 371. STEP_COUNTER_H register STEP_15 STEP_14 STEP_13 STEP_12 STEP_11 STEP_10 STEP_9 STEP_8 Table 372. STEP_COUNTER_H register description STEP_[15:8] Step counter output (MSbyte) LSM6DSV320X Embedded functions register description DS14623 - Rev 1 page 152/212 |
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