PDP83TG720SWCSTQ1 datasheet(171/199 Pages) TI

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7.6.2.113 PCS_STATUS_2 Register (Address = 0x3902) [reset = 0x0]

PCS_STATUS_2 is shown in Table 7-136.

Return to the Summary Table.

Table 7-136. PCS_STATUS_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

RESERVED

5b00000

Reserved

pcs_receive_link_status

1b0

1 = PCS receive link up 0 = PCS receive link down Note - 0x3 added

in [15:12] to differentiate

1b0 = PCS receive link down

1b1 = PCS receive link up

hi_rfer

1b0

1 = PCS reporting a high BER 0 = PCS not reporting a high BER

Note - 0x3 added in [15:12] to differentiate

1b0 = PCS not reporting a high BER

1b1 = PCS reporting a high BER

block_lock

1b0

1 = PCS locked to received blocks 0 = PCS not locked to received

blocks Note - 0x3 added in [15:12] to differentiate

1b0 = PCS not locked to received blocks

1b1 = PCS locked to received blocks

hi_rfer_lh

R/W0C

1b0

1 = PCS has reported a high BER 0 = PCS has not reported a high

BER Note - 0x3 added in [15:12] to differentiate

1b0 = PCS has not reported a high BER

1b1 = PCS has reported a high BER

block_lock_ll

R/W0S

1b0

1 = PCS has block lock 0 = PCS does not have block lock Note - 0x3

added in [15:12] to differentiate

1b0 = PCS does not have block lock

1b1 = PCS has block lock

5-0

ber_count

6b000000

BER counter Note - 0x3 added in [15:12] to differentiate

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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