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PDP83TG720SWCSTQ1 Datasheet(PDF) 170 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 170 Page - Texas Instruments |
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170 / 199 page ![]() 7.6.2.112 PCS_STATUS Register (Address = 0x3901) [reset = 0x0] PCS_STATUS is shown in Table 7-135. Return to the Summary Table. Table 7-135. PCS_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 4b0000 Reserved 11 tx_lpi_received_lh R/W0C 1b0 1 = Tx PCS has received LPI 0 = LPI not received Note - 0x3 added in [15:12] to differentiate 1b0 = LPI not received 1b1 = Tx PCS has received LPI 10 rx_lpi_received_lh R/W0C 1b0 1 = Rx PCS has received LPI 0 = LPI not received Note - 0x3 added in [15:12] to differentiate 1b0 = LPI not received 1b1 = Rx PCS has received LPI 9 tx_lpi_indication R 1b0 1 = Tx PCS is currently receiving LPI 0 = PCS is not currently receiving LPI Note - 0x3 added in [15:12] to differentiate 1b0 = PCS is not currently receiving LPI 1b1 = Tx PCS is currently receiving LPI 8 rx_lpi_indication R 1b0 1 = Rx PCS is currently receiving LPI 0 = PCS is not currently receiving LPI Note - 0x3 added in [15:12] to differentiate 1b0 = PCS is not currently receiving LPI 1b1 = Rx PCS is currently receiving LPI 7 pcs_fault R 1b0 1 = Fault condition detected 0 = No fault condition detected Note - 0x3 added in [15:12] to differentiate 1b0 = No fault condition detected 1b1 = Fault condition detected 6-3 RESERVED R 4b0000 Reserved 2 pcs_receive_link_status_ll R/W0S 1b0 1 = PCS receive link up 0 = PCS receive link down Note - 0x3 added in [15:12] to differentiate 1b0 = PCS receive link down 1b1 = PCS receive link up 1-0 RESERVED R 2b00 Reserved DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 170 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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