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PDP83TG720SWCSTQ1 Datasheet(PDF) 167 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 167 Page - Texas Instruments |
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167 / 199 page  7.6.2.109 TEST_MODE_CONTROL Register (Address = 0x1904) [reset = 0x0] TEST_MODE_CONTROL is shown in Table 7-132. Return to the Summary Table. Table 7-132. TEST_MODE_CONTROL Register Field Descriptions Bit Field Type Reset Description 15-13 cfg_test_mode R/W 3b000 111b = Test mode 7 110b = Test mode 6 101b = Test mode 5 100b = Test mode 4 011b = Reserved 010b = Test mode 2 001b = Test mode 1 000b = Normal (non-test) operation Note - 0x1 added in [15:12] to differentiate 3b000 = Normal (non-test) operation 3b001 = Test mode 1 3b010 = Test mode 2 3b011 = Reserved 3b100 = Test mode 4 3b101 = Test mode 5 3b110 = Test mode 6 3b111 = Test mode 7 12-0 RESERVED R 13b0000000 000000 Reserved www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 167 |
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