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PDP83TG720SWCSTQ1 Datasheet(PDF) 188 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 188 Page - Texas Instruments |
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188 / 199 page ![]() Figure 10-2. Power and Ground Plane Breaks 10.1.3 Physical Medium Attachment There must be no metal running beneath the common-mode choke. CMCs can inject noise into metal beneath them, which can affect the emissions and immunity performance of the system. Because the DP83TG720S-Q1 is a voltage mode line driver, no external termination resistors are required. The ESD shunt and MDI coupling capacitor should be connected to ground. Ensure that the common mode termination resistors are 1% tolerance or better to improve differential coupling. 10.1.4 Metal Pour All metal pours that are not signals or power must be tied to ground. There must be no floating metal in the system, and there must be no metal between differential traces. 10.1.5 PCB Layer Stacking To meet signal integrity and performance requirements, minimum four-layer PCB is recommended. However, a six-layer PCB and above should be used when possible. Figure 10-3. Recommended PCB Layer Stack-Up DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 188 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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