MCIMX6DP6AYM2AB datasheet(23/160 Pages) NXP

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

GPIO supplies10

NVCC_CSI,

NVCC_EIM0,

NVCC_EIM1,

NVCC_EIM2,

NVCC_ENET,

NVCC_GPIO,

NVCC_LCD,

NVCC_NANDF,

NVCC_SD1,

NVCC_SD2,

NVCC_SD3,

NVCC_JTAG

1.65

1.8,

2.8,

3.3

3.6

Isolation between the NVCC_EIMx and

NVCC_SDx different supplies allow them to

operate at different voltages within the specified

range.

Example: NVCC_EIM1 can operate at 1.8 V

while NVCC_EIM2 operates at 3.3 V.

NVCC_LVDS_2P511

NVCC_MIPI

2.25

2.5

2.75

—

HDMI supply voltages

HDMI_VP

0.99

1.1

1.3

—

HDMI_VPH

2.25

2.5

2.75

—

PCIe supply voltages

PCIE_VP

1.023

1.1

1.3

—

PCIE_VPH

2.325

2.5

2.75

—

PCIE_VPTX

1.023

1.1

1.3

—

SATA Supply voltages

SATA_VP

0.99

1.1

1.3

—

SATA_VPH

2.25

2.5

2.75

—

Junction temperature

-40

105

°CSee i.MX 6Dual/6Quad Product Lifetime Usage

Estimates Application Note, AN4724, for

information on product lifetime (power-on

years) for this processor.

1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set

point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.

2 See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs.

3 For Quad core system, connect to VDD_ARM_IN. For Dual core system, may be shorted to GND together with

VDD_ARM23_CAP to reduce leakage.

4 VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation.

5 VDD_ARM_CAP must not exceed VDD_CACHE_CAP by more than +50 mV. VDD_CACHE_CAP must not exceed

VDD_ARM_CAP by more than 200 mV.

6 VDD_SOC_CAP and VDD_PU_CAP must be equal.

7 In LDO enabled mode, the internal LDO output set points must be configured such that the:

VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV.

VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point.

The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set

points shown in this table must be maintained.

8 In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more

than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages

shown in this table must be maintained.

9 To set VDD_SNVS_IN voltage with respect to Charging Currents and RTC, see the Hardware Development Guide for i.MX

6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

Table 6. Operating Ranges (continued)

Parameter

Description

Symbol

Min

Typ

Max1

Unit

Comment2

MCIMX6DP6AYM2AB Datasheet(PDF) 23 Page - NXP Semiconductors

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