MCIMX6DP6AYM2AB datasheet(46/160 Pages) NXP

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i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

4.7.3

LVDS I/O AC Parameters

The differential output transition time waveform is shown in Figure 6.

Figure 6. Differential LVDS Driver Transition Time Waveform

Table 30 shows the AC parameters for LVDS I/O.

Single output slew rate, measured between

Vol(ac) and Voh(ac)

tsr

Driver impedance =

2.5

—

V/ns

Skew between pad rise/fall asymmetry +

skew caused by SSN

tSKD

clk = 533 MHz

——

0.1

1 Note that the JEDEC JESD79_3C specification supersedes any specification in this document.

2 Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).

3 The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Table 30. I/O AC Parameters of LVDS Pad

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Differential pulse skew1

1 t

SKD = | tPHLD –tPLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

tSKD

Rload = 100

Ω,

Cload = 2 pF

—

0.25

Transition Low to High Time2

2 Measurement levels are 20–80% from output voltage.

tTLH

——

0.5

Transition High to Low Time2

tTHL

——

0.5

Operating Frequency

—

600

800

MHz

Offset voltage imbalance

Vos

—

150

Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters1 (continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

padp

padn

VDIFF

0V (Differential)

VDIFF = {padp} - {padn}

tTLH

20%

80%

20%

80%

tTHL

VOH

VOL

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