MCIMX6DP6AYM2AB datasheet(94/160 Pages) NXP

94 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

4.12.10.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.12.10.2.1 BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals. The

timing syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is IPU2_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the

data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital

blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding

from the data stream, thus recovering IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals for internal

use. On BT.656 one component per cycle is received over the IPU2_CSIx_DATA_EN bus. On BT.1120

two components per cycle are received over the IPU2_CSIx_DATA_EN bus.

4.12.10.2.2 Gated Clock Mode

The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this

mode. See Figure 57.

Figure 57. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on IPU2_CSIx_VSYNC (all the timings correspond to straight polarity

of the corresponding signals). Then IPU2_CSIx_HSYNC goes to high and hold for the entire line. Pixel

clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel

clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI

2 The MSB bits are duplicated on LSB bits implementing color extension.

3 The two MSB bits are duplicated on LSB bits implementing color extension.

4 YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).

5 RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly

processing, but only under some restrictions on the control protocol.

6 YCbCr, 16 bits—Supported as a “generic-data” input—with no on-the-fly processing.

7 YCbCr, 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

8 YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

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