MCIMX6DP6AYM2AB datasheet(10/160 Pages) NXP

10 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Modules List

CSI

MIPI CSI-2 Interface Multimedia

Peripherals

The CSI IP provides MIPI CSI-2 standard camera interface port. The

CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800

Mbps for 4 data lanes.

CSU

Central Security Unit Security

The Central Security Unit (CSU) is responsible for setting comprehensive

security policy within the i.MX 6DualPlus/6QuadPlus platform. The

Security Control Registers (SCR) of the CSU are set during boot time by

the HAB and are locked to prevent further writing.

CTI-0

CTI-1

CTI-2

CTI-3

CTI-4

Cross Trigger

Interfaces

Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from

masters attached to CTIs. The CTI module is internal to the Cortex-A9

Core Platform.

CTM

Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.

The CTM module is internal to the Cortex-A9 Core Platform.

DAP

Debug Access Port

System

Control

Peripherals

The DAP provides real-time access for the debugger without halting the

core to:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan chains. The DAP

module is internal to the Cortex-A9 Core Platform.

DCIC-0

DCIC-1

Display Content

Integrity Checker

Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX

6DualPlus/6QuadPlus processor has two such modules, one for each

IPU.

DSI

MIPI DSI interface

Multimedia

Peripherals

The MIPI DSI IP provides DSI standard display port interface. The DSI

interface support 80 Mbps to 1 Gbps speed per data lane.

eCSPI1-5

Configurable SPI

Connectivity

Peripherals

Full-duplex enhanced Synchronous Serial Interface. It is configurable to

support Master/Slave modes, four chip selects to support multiple

peripherals.

ENET

Ethernet Controller

Connectivity

Peripherals

The Ethernet Media Access Controller (MAC) is designed to support

10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external

transceiver interface and transceiver function are required to complete the

interface to the media. The i.MX 6DualPlus/6QuadPlus processors also

consist of hardware assist for IEEE 1588 standard. For details, see the

ENET chapter of the i.MX 6DualPlus/6QuadPlus reference manual

(IMX6DQPRM).

Note: The theoretical maximum performance of 1 Gbps ENET is limited

to 470 Mbps (total for Tx and Rx) due to internal bus throughput

limitations. The actual measured performance in optimized environment

is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX

6Dual/6Quad errata document (IMX6DQCE).

EPIT-1

EPIT-2

Enhanced Periodic

Interrupt Timer

Timer

Peripherals

Each EPIT is a 32-bit “set and forget” timer that starts counting after the

EPIT is enabled by software. It is capable of providing precise interrupts

at regular intervals with minimal processor intervention. It has a 12-bit

prescaler for division of input clock frequency to get the required time

setting for the interrupts to occur, and counter value can be programmed

on the fly.

Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

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