MCIMX6DP6AYM2AB datasheet(6/160 Pages) NXP

6 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Introduction

— One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY

— Three USB 2.0 (480 Mbps) hosts:

– One HS host with integrated High Speed PHY

– Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY

•

Expansion PCI Express port (PCIe) v2.0 one lane

— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint

operations. Uses x1 PHY configuration.

•

Miscellaneous IPs and interfaces:

— SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and

outputs with I2S mode

— ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with

7.1 multi channel outputs

— Five UARTs, up to 5.0 Mbps each:

– Providing RS232 interface

– Supporting 9-bit RS485 multidrop mode

– One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This

is due to the SoC IOMUX limitation, because all UART IPs are identical.

— Five eCSPI (Enhanced CSPI)

— Three I2C, supporting 400 kbps

— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps

— Four Pulse Width Modulators (PWM)

— System JTAG Controller (SJC)

— GPIO with interrupt capabilities

— 8x8 Key Pad Port (KPP)

— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx

— Two Controller Area Network (FlexCAN), 1 Mbps each

— Two Watchdog timers (WDOG)

— Audio MUX (AUDMUX)

The i.MX 6DualPlus/6QuadPlus processors integrate advanced power management unit and controllers:

•

Provide PMU, including LDO supplies, for on-chip resources

•

Use Temperature Sensor for monitoring the die temperature

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Support DVFS techniques for low power modes

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Use Software State Retention and Power Gating for Arm and MPE

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Support various levels of system power modes

•

Use flexible clock gating control scheme

1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus

throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the

ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).

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