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MCIMX6DP6AYM2AB Datasheet(PDF) 47 Page - NXP Semiconductors |
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MCIMX6DP6AYM2AB Datasheet(HTML) 47 Page - NXP Semiconductors |
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47 / 160 page  Electrical Characteristics i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 NXP Semiconductors 47 4.8 Output Buffer Impedance Parameters This section defines the I/O impedance parameters of the i.MX 6DualPlus/6QuadPlus processors for the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes •LVDS I/O NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 7). |
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