MCIMX6DP6AYM2AB datasheet(95/160 Pages) NXP

95 / 160 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the

next frame, the IPU2_CSIx_VSYNC timing repeats.

4.12.10.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.12.10.2.2, “Gated Clock Mode,”)

except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 58). All incoming pixel clocks

are valid and cause data to be latched into the input FIFO. The IPU2_CSIx_PIX_CLK signal is inactive

(states low) until valid data is going to be transmitted over the bus.

Figure 58. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 58 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered

IPU2_CSIx_VSYNC; active-high/low IPU2_CSIx_HSYNC; and rising/falling-edge triggered

IPU2_CSIx_PIX_CLK.

IPU2_CSIx_VSYNC

IPU2_CSIx_PIX_CLK

IPU2_CSIx_DATA_EN[19:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Start of Frame

MCIMX6DP6AYM2AB Datasheet(PDF) 95 Page - NXP Semiconductors