MCIMX6DP6AYM2AB datasheet(1/160 Pages) NXP

Part #	MCIMX6DP6AYM2AB

Description	i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products

PDF	160 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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NXP Semiconductors

Data Sheet: Technical Data

Document Number: IMX6DQPIEC

Rev. 3, 11/2018

Package Information

FCPBGA Package

21 x 21 mm, 0.8 mm pitch

NXP Reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Ordering Information

See Table 1

MCIMX6QPxCxxxxA

MCIMX6QPxCxxxxB

MCIMX6DPxCxxxxA

MCIMX6DPxCxxxxB

1

Introduction

The i.MX 6DualPlus/6QuadPlus processors offer the

highest levels of graphics processing performance in the

i.MX 6 series family and are ideally suited for graphics

intensive applications.

The i.MX 6DualPlus/6QuadPlus processors feature

advanced implementation of the quad

Arm® Cortex®-A9 core, which operates at speeds up to

800 MHz. They include updated versions of the 2D and

3D graphics processors, 1080p video processing, and

integrated power management. Each processor provides

a 64-bit DDR3/DDR3L/LPDDR2-800 memory interface

and a number of other interfaces for connecting

peripherals, such as WLAN, Bluetooth®, GPS, hard

drive, displays, and camera sensors.

The i.MX 6DualPlus/6QuadPlus processors are

specifically useful for applications such as the

following:

•

Graphics rendering for Human Machine

Interfaces (HMI)

•

Video processing and display

i.MX 6DualPlus/6QuadPlus

Applications Processors

Industrial Products

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3

Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7

2

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

Special Signal Considerations. . . . . . . . . . . . . . . . 19

3.2

Recommended Connections for Unused Analog

Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1

Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20

4.2

Power Supplies Requirements and Restrictions . . 33

4.3

Integrated LDO Voltage Regulator Parameters . . 34

4.4

PLL Electrical Characteristics . . . . . . . . . . . . . . . . 36

4.5

On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 37

4.6

I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38

4.7

I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44

4.8

Output Buffer Impedance Parameters. . . . . . . . . . 49

4.9

System Modules Timing . . . . . . . . . . . . . . . . . . . . 53

4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 64

4.11 General-Purpose Media Interface (GPMI) Timing. 64

4.12 External Peripheral Interface Parameters . . . . . . . 73

5

Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 138

5.1

Boot Mode Configuration Pins. . . . . . . . . . . . . . . 138

5.2

Boot Devices Interfaces Allocation . . . . . . . . . . . 139

6

Package Information and Contact Assignments . . . . . . 141

6.1

Signal Naming Convention . . . . . . . . . . . . . . . . . 141

6.2

21 x 21 mm Package Information . . . . . . . . . . . . 141

7

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

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