MCIMX6DP6AYM2AB datasheet(71/160 Pages) NXP

71 / 160 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For DDR

Toggle mode, the typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI

will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX

6DualPlus/6QuadPlus reference manual (IMX6DQPRM)). Generally, the typical delay value is equal to

0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot

be ignored, the delay value should be made larger to compensate the board delay.

4.12

External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.12.1

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.12.2

ECSPI Timing Parameters

This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing

parameters for master and slave modes.

NF28 Data write setup

tDS6

0.25

× tCK - 0.32

—

NF29 Data write hold

tDH6

0.25

× tCK - 0.79

—

NF30 NAND_DQS/NAND_DQ read setup skew

tDQSQ7

—3.18

—

NF31 NAND_DQS/NAND_DQ read hold skew

tQHS7

—3.27

—

1 The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

AS minimum value can be 0, while DS/DH minimum value is 1.

3 T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

4 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is met automatically by the design. Read/Write operation is

started with enough time of ALE/CLE assertion to low level.

5 PRE_DELAY+1)

≥ (AS+DS).

6 Shown in Figure 28.

7 Shown in Figure 29.

Table 42. Samsung Toggle Mode Timing Parameters1 (continued)

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min

Max

MCIMX6DP6AYM2AB Datasheet(PDF) 71 Page - NXP Semiconductors

MCIMX6DP6AYM2AB Datasheet(HTML) 71 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL