MCIMX6DP6AYM2AB datasheet(28/160 Pages) NXP

28 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

STOP_OFF

• Arm LDO set to 0.9 V

• SoC LDO set to 1.225 V

• PU LDO is power gated

• HIGH LDO set to 2.5 V

• PLLs disabled

• DDR is in self refresh

VDD_ARM_IN (1.4 V)

7.5

VDD_SOC_IN (1.4 V)

13.5

VDD_HIGH_IN (3.0 V)

3.7

Total

STANDBY

• ARM and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5 V

• PLLs are disabled

• Low voltage

• Well Bias ON

• Crystal oscillator is enabled

VDD_ARM_IN (0.9 V)

0.1

VDD_SOC_IN (1.05 V)

VDD_HIGH_IN (3.0 V)

3.7

Total

Deep Sleep Mode

(DSM)

• ARM and PU LDOs are power gated

• SoC LDO is in bypass

• HIGH LDO is set to 2.5 V

• PLLs are disabled

• Low voltage

• Well Bias ON

• Crystal oscillator and bandgap are disabled

VDD_ARM_IN (0.9 V)

0.1

VDD_SOC_IN (1.05 V)

VDD_HIGH_IN (3.0 V)

0.5

Total

3.4

SNVS Only

• VDD_SNVS_IN powered

• All other supplies off

• SRTC running

VDD_SNVS_IN (2.8V)

μA

Total

115

μW

1 The typical values shown here are for information only and are not guaranteed. These values are average values measured

on a worst-case wafer at 25

°C.

Table 9. Stop Mode Current and Power Consumption (continued)

Mode

Test Conditions

Supply

Typical1

Unit

MCIMX6DP6AYM2AB Datasheet(PDF) 28 Page - NXP Semiconductors

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