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MCIMX6DP6AYM2AB Datasheet(PDF) 53 Page - NXP Semiconductors |
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MCIMX6DP6AYM2AB Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 160 page  Electrical Characteristics i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 NXP Semiconductors 53 4.9.3.2 General EIM Timing-Synchronous Mode Figure 10, Figure 11, and Table 37 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields. Figure 10. EIM Output Timing Diagram Figure 11. EIM Input Timing Diagram 4.9.3.3 Examples of EIM Synchronous Accesses Table 37. EIM Bus Timing Parameters ID Parameter Min1 Max1 Unit WE1 EIM_BCLK cycle time2 t × (k+1) — ns WE2 EIM_BCLK high level width 0.4 × t × (k+1) — ns WE3 EIM_BCLK low level width 0.4 × t × (k+1) — ns WE4 EIM_ADDRxx EIM_CSx_B EIM_WE_B EIM_OE_B EIM_BCLK EIM_EBx_B EIM_LBA_B Output Data ... WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE3 WE2 WE1 Input Data EIM_WAIT_B EIM_BCLK WE19 WE18 WE21 WE20 |
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