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MCIMX6DP6AYM2AB Datasheet(PDF) 45 Page - NXP Semiconductors

Part # MCIMX6DP6AYM2AB
Description  i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products
PDF  160 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MCIMX6DP6AYM2AB Datasheet(HTML) 45 Page - NXP Semiconductors

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Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018
NXP Semiconductors
45
4.7.2
DDR I/O AC Parameters
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
Table 28 shows the AC parameters for DDR I/O operating in LPDDR2 mode.
Table 29 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
Table 28. DDR I/O LPDDR2 Mode AC Parameters1
1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
—
Vref + 0.22
—
OVDD
V
AC input logic low
Vil(ac)
—
0
—
Vref – 0.22
V
AC differential input high voltage2
2 Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
Vidh(ac)
—
0.44
—
—
V
AC differential input low voltage
Vidl(ac)
—
—
—
0.44
V
Input AC differential cross point voltage3
3 The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Vix(ac)
Relative to Vref
-0.12
—
0.12
V
Over/undershoot peak
Vpeak
—
—
—
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
400 MHz
—
—
0.2
V-ns
Single output slew rate, measured
between Vol(ac) and Voh(ac)
tsr
50
Ω to Vref.
5 pF load.
Drive impedance = 4 0
Ω ±30%
1.5
—
3.5
V/ns
50
Ω to Vref.
5pF load.
Drive impedance = 60
Ω ±30%
1—
2.5
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk = 400 MHz
——
0.1
ns
Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
—
Vref + 0.175
—
OVDD
V
AC input logic low
Vil(ac)
—
0
—
Vref – 0.175
V
AC differential input voltage2
Vid(ac)
—
0.35
—
—
V
Input AC differential cross point voltage3
Vix(ac)
Relative to Vref
Vref – 0.15
—
Vref + 0.15
V
Over/undershoot peak
Vpeak
—
—
—
0.4
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
533 MHz
—
—
0.5
V-ns



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