MCIMX6DP6AYM2AB datasheet(79/160 Pages) NXP

79 / 160 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

4.12.4.2 eMMC4.4/4.41 (Dual Data Rate) eSDHCv3 AC Timing

Figure 38 depicts the timing of eMMC4.4/4.41. Table 47 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only SDx_DATAx is sampled on both edges of the clock (not applicable to SD_CMD).

Figure 38. eMMC4.4/4.41 Timing

eSDHC Input/Card Outputs SD_CMD, SD_DATAx (Reference to SDx_CLK)

SD7

eSDHC Input Setup Time

tISU

2.5

—

SD8

eSDHC Input Hold Time4

tIH

1.5

—

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0

–50 MHz.

3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

4To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 47. eMMC4.4/4.41 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock1

1 Clock duty cycle will be in the range of 47% to 53%.

SD1

Clock Frequency (EMMC4.4 DDR)

fPP

052

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

050

MHz

uSDHC Output / Card Inputs SD_CMD, SD_DATAx (Reference to SD_CLK)

SD2

uSDHC Output Delay

tOD

2.8

6.8

uSDHC Input / Card Outputs SD_CMD, SD_DATAx (Reference to SD_CLK)

SD3

uSDHC Input Setup Time

tISU

1.7

—

SD4

uSDHC Input Hold Time

tIH

1.5

—

Table 46.

SD/eMMC4.3 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD3

Output from eSDHCv3 to card

Input from card to eSDHCv3

SDx_DATA[7:0]

SDx_CLK

SD4

SD2

......

SDx_DATA[7:0]

SD2

MCIMX6DP6AYM2AB Datasheet(PDF) 79 Page - NXP Semiconductors

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