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MCIMX6DP6AYM2AB Datasheet(PDF) 32 Page - NXP Semiconductors |
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MCIMX6DP6AYM2AB Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 160 page ![]() i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 32 NXP Semiconductors Electrical Characteristics 4.2 Power Supplies Requirements and Restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: • Excessive current during power-up phase • Prevention of the device from booting • Irreversible damage to the processor 4.2.1 Power-Up Sequence For power-up sequence, the restrictions are as follows: • VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected (shorted) with VDD_HIGH_IN supply. • If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on. • The SRC_POR_B signal controls the processor POR and must be immediately asserted at power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no restrictions. NOTE Ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies). NOTE USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply sequence and can be powered at any time. 4.2.2 Power-Down Sequence There are no special restrictions for i.MX 6DualPlus/6QuadPlus SoC. 4.2.3 Power Supplies Usage • All I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see the “Power Group” column of Table 87, “21 x 21 mm Functional Contact Assignments”. • When the SATA interface is not used, the SATA_VP and SATA_VPH supplies should be grounded. The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N, SATA_PHY_RX_P, and SATA_PHY_TX_N) can remain unconnected. It is recommended not to turn OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive |
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