MCIMX6DP6AYM2AB datasheet(99/160 Pages) NXP

99 / 160 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

There are special physical outputs to provide synchronous controls:

•

The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

•

The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC)

calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control

starts from the local start point with predefined UP and DOWN values to calculate control’s changing

points with half DI_CLK resolution. A full description of the counter system can be found in the IPU

chapter of the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).

4.12.10.5.2 Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to

additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

•

The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.

•

The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any other data-oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals

toggling. When a DI decides to put a new asynchronous data on the bus, a

new internal start (local start point) is generated. The signal generators

calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

4.12.10.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.12.10.6.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

•

IPP_DISP_CLK—Clock to display

•

HSYNC—Horizontal synchronization

•

VSYNC—Vertical synchronization

•

DRDY—Active data

All synchronous display controls are generated on the base of an internally generated “local start point”.

The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.

The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved

relative to the local start point. The data bus of the synchronous interface is output direction only.

MCIMX6DP6AYM2AB Datasheet(PDF) 99 Page - NXP Semiconductors

MCIMX6DP6AYM2AB Datasheet(HTML) 99 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL