MCIMX6DP6AYM2AB datasheet(27/160 Pages) NXP

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

4.1.6

Low Power Mode Supply Currents

Table 9 shows the current core consumption (not including I/O) of the i.MX 6DualPlus/6QuadPlus

processors in selected low power modes.

MISC

DRAM_VREF

—

1 i.MX 6DualPlus numbers assume VDD_ARM23_IN and VDD_ARM23_CAP are connected to ground.

2 The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the

VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or

HDMI, PCIe, and SATA VPH supplies).

3 Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN

current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of

the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that

current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.

4 This is the maximum current per active USB physical interface.

5 The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators

are typically available from memory vendors which take into account factors such as signal termination.

See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for examples of DRAM power

consumption during specific use case scenarios.

6 General equation for estimated, maximum power consumption of an IO power supply:

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

Table 9. Stop Mode Current and Power Consumption

Mode

Test Conditions

Supply

Typical1

Unit

WAIT

• Arm, SoC, and PU LDOs are set to 1.225 V

• HIGH LDO set to 2.5 V

• Clocks are gated

• DDR is in self refresh

• PLLs are active in bypass (24 MHz)

• Supply voltages remain ON

VDD_ARM_IN (1.4 V)

VDD_SOC_IN (1.4 V)

VDD_HIGH_IN (3.0 V)

3.7

Total

STOP_ON

• Arm LDO set to 0.9 V

• SoC and PU LDOs set to 1.225 V

• HIGH LDO set to 2.5 V

• PLLs disabled

• DDR is in self refresh

VDD_ARM_IN (1.4 V)

7.5

VDD_SOC_IN (1.4 V)

VDD_HIGH_IN (3.0 V)

3.7

Total

Table 8. Maximum Supply Currents (continued)

Power Supply

Conditions

Maximum Current

Unit

Power Virus

CoreMark

MCIMX6DP6AYM2AB Datasheet(PDF) 27 Page - NXP Semiconductors

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