MCIMX6DP6AYM2AB datasheet(51/160 Pages) NXP

51 / 160 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

4.9.2

WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 35 lists the timing parameters.

Figure 9. WDOG1_B Timing Diagram

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30

μs.

NOTE

WDOG1_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the IOMUX

manual for detailed information.

4.9.3

External Interface Module (EIM)

The following subsections provide information on the EIM. Maximum operating frequency for EIM data

transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings or

clock periods are valid for the entire range of allowed frequencies (0–104 MHz).

Table 34. Reset Timing Parameters

Parameter

Min

Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid

—

XTALOSC_RTC_ XTALI cycle

Table 35. WDOG1_B Timing Parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOG1_B Assertion

—

XTALOSC_RTC_ XTALI cycle

WDOG1_B

CC3

(Output)

MCIMX6DP6AYM2AB Datasheet(PDF) 51 Page - NXP Semiconductors