DSP56307SLASHD datasheet(5/156 Pages) MOTOROLA

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DSP56307

Target Applications

MOTOROLA

DSP56307 Technical Data

On-Chip Peripherals

Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses

(e.g., ISA) and provides glueless connection to a number of industry-standard

microcomputers, microprocessors, and DSPs

Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three

transmitters (allows six-channel home theater)

Serial communications interface (SCI) with baud rate generator

Triple timer module

Up to 34 programmable general purpose input/output (GPIO) pins, depending on which

peripherals are enabled

Reduced Power Dissipation

Very low power CMOS design

Wait and Stop low-power standby modes

Fully static logic, operation frequency down to 0 Hz (dc)

Optimized power management circuitry (instruction-dependent, peripheral-dependent,

and mode-dependent)

TARGET APPLICATIONS

The DSP56307 is intended for applications requiring a large amount of on-chip memory, such as

wireless infrastructure applications. The EFCOP may be used to accelerate general filtering

applications, such as echo-cancellation applications, correlation, and general purpose

convolution-based algorithms.

Not Recommended for New Design

DSP56307/D Datasheet(PDF) 5 Page - Motorola, Inc