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DSP56307/D Datasheet(PDF) 64 Page - Motorola, Inc |
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DSP56307/D Datasheet(HTML) 64 Page - Motorola, Inc |
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64 / 156 page  2-28 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3, 4 No. Characteristics Symbol Expression 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 131 Page mode cycle time tPC 4.5 × T C 68.2 Ñ 56.3 Ñ 45.0 Ñ ns 132 CAS assertion to data valid (read) tCAC 66 MHz : 2.75 × T C − 7.5 80 MHz : 2.75 × T C − 6.5 100 MHz : 2.75 × T C − 5.7 Ñ Ñ Ñ 34.2 Ñ Ñ Ñ Ñ Ñ Ñ 27.9 Ñ Ñ Ñ Ñ Ñ Ñ 21.8 ns ns ns 133 Column address valid to data valid (read) tAA 66 MHz : 3.75 × T C − 7.5 80 MHz : 3.75 × T C − 6.5 100 MHz : 3.75 × T C − 5.7 Ñ Ñ Ñ 49.3 Ñ Ñ Ñ Ñ Ñ Ñ 40.4 Ñ Ñ Ñ Ñ Ñ Ñ 31.8 ns ns ns 134 CAS deassertion to data not valid (read hold time) tOFF Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns 135 Last CAS assertion to RAS deassertion tRSH 3.5 × T C − 4.0 49.0 Ñ 39.8 Ñ 31.0 Ñ ns 136 Previous CAS deassertion to RAS deassertion tRHCP 6 × TC − 4.0 86.9 Ñ 71.0 Ñ 56.0 Ñ ns 137 CAS assertion pulse width tCAS 2.5 × T C − 4.0 33.9 Ñ 27.3 Ñ 21.0 Ñ ns 138 Last CAS deassertion to RAS deassertion5 ¥ BRW[1:0] = 00 ¥ BRW[1:0] = 01 ¥ BRW[1:0] = 10 ¥ BRW[1:0] = 11 tCRP 2.75 × T C − 6.0 4.25 × T C − 6.0 5.25 × T C − 6.0 6.25 × T C − 6.0 35.8 58.6 73.8 89.0 Ñ Ñ Ñ Ñ 28.4 47.2 59.7 72.2 Ñ Ñ Ñ Ñ 21.5 36.5 46.5 56.5 Ñ Ñ Ñ Ñ ns ns ns ns 139 CAS deassertion pulse width tCP 2 × T C − 4.0 26.3 Ñ 21.0 Ñ 16.0 Ñ ns 140 Column address valid to CAS assertion tASC TC − 4.0 11.2 Ñ 8.5 Ñ 6.0 Ñ ns 141 CAS assertion to column address not valid tCAH 3.5 × T C − 4.0 49.0 Ñ 39.8 Ñ 31.0 Ñ ns 142 Last column address valid to RAS deassertion tRAL 5 × T C − 4.0 71.8 Ñ 58.5 Ñ 46.0 Ñ ns 143 WR deassertion to CAS assertion tRCS 1.25 × T C − 3.8 15.1 Ñ 11.8 Ñ 8.7 Ñ ns 144 CAS deassertion to WR assertion tRCH 1.25 × T C − 3.7 15.2 Ñ 11.9 Ñ 8.8 Ñ ns Not Recommended for New Design |
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