DSP56307SLASHD datasheet(79/156 Pages) MOTOROLA

79 / 156 page

Specifications

External Memory Interface (Port A)

MOTOROLA

DSP56307 Technical Data

2-43

187 RAS assertion to data not

valid (write)

tDHR

9.75

× T

C − 4.0

143.7

117.9

93.5

188 WR assertion to CAS

assertion

tWCS

9.5

× T

C − 4.3

139.6

114.5

90.7

189 CAS assertion to RAS

assertion (refresh)

tCSR

1.5

× T

C − 4.0

18.7

14.8

11.0

190 RAS deassertion to CAS

assertion (refresh)

tRPC

4.75

× T

C − 4.0

68.0

55.4

43.5

191 RD assertion to RAS

deassertion

tROH

15.5

× T

C − 4.0

230.8

189.8

151.0

192 RD assertion to data valid

tGA

66 MHz

× T

C − 7.5

80 MHz

× T

C − 6.5

100 MHz

× T

C − 5.7

204.6

168.5

134.3

193 RD deassertion to data not

valid3

tGZ

0.0

194 WR assertion to data active

0.75

× T

C − 0.3

11.1

9.1

7.2

195 WR deassertion to data high

impedance

0.25

× T

3.8

3.1

2.5

Notes:

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not

tGZ.

Either tRCH or tRRH must be satisfied for read cycles.

Table 2-16

DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued)

No.

Characteristics3

Symbol

Expression

66 MHz

80 MHz

100 MHz

Unit

Min Max Min Max Min Max

Not Recommended for New Design

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