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DSP56307/D Datasheet(PDF) 8 Page - Motorola, Inc |
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DSP56307/D Datasheet(HTML) 8 Page - Motorola, Inc |
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8 / 156 page  1-2 DSP56307 Technical Data MOTOROLA Signals/Connections Signal Groupings Figure 1-1 Signals Identified by Functional Group DSP56307 24 18 External Address Bus External Data Bus External Bus Control Enhanced Synchronous Serial Interface Port 0 (ESSI0)2 Timers3 PLL OnCE/JTA G Port Power Inputs: PLL Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer A0–A17 D0–D23 AA0–AA3/ RAS0–RAS3 RD WR TA BR BG BB CAS BCLK BCLK TCK TDI TDO TMS TRST DE CLKOUT PCAP After Reset NMI VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS 4 Serial Communications Interface (SCI) Port2 4 2 2 Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS 4 4 4 2 Interrupt/M ode Control MODA MODB MODC MODD RESET Host Interface (HI08) Port1 Non-Multiplexe d Bus H0–H7 HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HREQ/HREQ HACK/HACK RXD TXD SCLK SC00–SC02 SCK0 SRD0 STD0 TIO0 TIO1 TIO2 8 3 3 2 EXTAL XTAL Clock Enhanced Synchronous Serial Interface Port 1 (ESSI1)2 SC10–SC12 SCK1 SRD1 STD1 3 Multiplexed Bus HAD0–HAD7 HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ Port B GPIO PB0–PB7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port E GPIO PE0 PE1 PE2 Port C GPIO PC0–PC2 PC3 PC4 PC5 Port D GPIO PD0–PD2 PD3 PD4 PD5 Timer GPIO TIO0 TIO1 TIO2 Port A 4 AA0601 Note: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0–PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity. 2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0–PC5), Port D GPIO signals (PD0–PD5), and Port E GPIO signals (PE0–PE2), respectively. 3. TIO0–TIO2 can be configured as GPIO signals. IRQA IRQB IRQC IRQD PINIT 3 RESET During Reset After Reset Reset During Not Recommended for New Design |
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