DSP56307SLASHD datasheet(55/156 Pages) MOTOROLA

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Specifications

External Memory Interface (Port A)

MOTOROLA

DSP56307 Technical Data

2-19

109 Data hold time from

WR deassertion

tDH

100 MHz:

0.25

× T

C − 2.4 [1 ≤ WS ≤ 3]

All frequencies:

1.25

× T

C − 3.8 [4 ≤ WS ≤ 7]

2.25

× T

C − 3.8 [WS ≥ 8]

0.1

8.7

18.7

110 WR assertion to data

active

0.75

× T

C − 3.7 [WS = 1]

0.25

× T

C − 3.7 [2 ≤ WS ≤ 3]

−0.25 × T

C − 3.7 [WS ≥ 4]

3.8

Ð1.2

Ð6.2

111 WR deassertion to

data high

impedance

0.25

× T

C + 0.2 [1 ≤ WS ≤ 3]

1.25

× T

C + 0.2 [4 ≤ WS ≤ 7]

2.25

× T

C + 0.2 [WS ≥ 8]

2.7

12.7

22.7

112 Previous RD

deassertion to data

active (write)

1.25

× T

C − 4.0 [1 ≤ WS ≤ 3]

2.25

× T

C − 4.0 [4 ≤ WS ≤ 7]

3.25

× T

C − 4.0 [WS ≥ 8]

8.5

18.5

28.5

113 RD deassertion time

0.75

× T

C − 4.0 [1 ≤ WS ≤ 3]

1.75

× T

C − 4.0 [4 ≤ WS ≤ 7]

2.75

× T

C − 4.0 [WS ≥ 8]

3.5

13.5

23.5

114 WR deassertion

time

0.5

× T

C − 3.5 [WS = 1]

TC − 3.5 [2 ≤ WS ≤ 3]

2.5

× T

C − 3.5 [4 ≤ WS ≤ 7]

3.5

× T

C − 3.5 [WS ≥ 8]

1.5

6.5

21.5

31.5

115 Address valid to RD

assertion

0.5

× T

C − 4

1.0

116 RD assertion pulse

width

(WS + 0.25)

× T

C − 3.8

8.7

117 RD deassertion to

address not valid

0.25

× T

C − 3.0 [1 ≤ WS ≤ 3]

1.25

× T

C − 3.0 [4 ≤ WS ≤ 7]

2.25

× T

C − 3.0 [WS ≥ 8]

0.0

9.5

19.5

Notes:

WS is the number of wait states specified in the BCR.

VCCQL = 2.5 V ± 0.25 V; TJ = Ð40ûC to +100 ûC, CL = 50 pF

Table 2-8

SRAM Read and Write Accesses (Continued)

No.

Characteristics

Symbol

Expression1, 2

100 MHz

Unit

Min

Max

Not Recommended for New Design

DSP56307/D Datasheet(PDF) 55 Page - Motorola, Inc

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