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DSP56307/D Datasheet(PDF) 10 Page - Motorola, Inc

Part # DSP56307/D
Description  24-BIT DIGITAL SIGNAL PROCESSOR
PDF  156 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56307/D Datasheet(HTML) 10 Page - Motorola, Inc

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DSP56307 Technical Data
MOTOROLA
Signals/Connections
Ground
GROUND
Table 1-3
Grounds
Ground
Name
Description
GNDP
PLL Ground
ÑGNDP is ground-dedicated for PLL use. The connection should be
provided with an extremely low-impedance path to ground. VCCP should be
bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip
package.
GNDP1
PLL Ground 1
ÑGNDP1 is ground-dedicated for PLL use. The connection should be
provided with an extremely low-impedance path to ground.
GNDQ
Quiet Ground
ÑGNDQ is an isolated ground for the internal processing logic. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
GNDA
Address Bus Ground
ÑGNDA is an isolated ground for sections of the address bus
I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors. There
are four GNDA connections.
GNDD
Data Bus Ground
ÑGNDD is an isolated ground for sections of the data bus I/O
drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GNDC
Bus Control Ground
ÑGNDC is an isolated ground for the bus control I/O drivers.
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors.
GNDH
Host Ground
ÑGNDH is an isolated ground for the HI08 I/O drivers. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
GNDS
ESSI, SCI, and Timer Ground
ÑGNDS is an isolated ground for the ESSI, SCI, and
timer I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Not Recommended for New Design



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