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HC805K3GRS/D Datasheet(PDF) 33 Page - NXP Semiconductors |
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HC805K3GRS/D Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 119 page  General Release Specification Mask Option Registers (MOR) $0012 and $0013 MC68HC805K3 — Rev. 1.0 Memory Map 33 COPEN — COP Enable/Disable READ: Any time WRITE: In user mode, writing has no effect. 1 = The COP is enabled 0 = The COP is disabled (erased state) LEVIRQ — Interrupt Request Option READ: Any time WRITE: In user mode, writing has no effect. 1 = The IRQ pin is edge and level sensitive 0 = The IRQ pin is edge sensitive (erased state) PIRQ — Port A IRQ Enable READ: Any time. WRITE: In user mode, writing has no effect. 1 = PA3 through PA0 enabled as external interrupt sources 0 = PA3 through PA0 not enabled as external interrupt sources (erased state) SWPDI — Software Pulldown Inhibit READ: Any time WRITE: In user mode, writing has no effect. 1 = The software pulldown is disabled 0 = The software pulldown is enabled (erased state) HALT — STOP Conversion to Halt Mode READ: Any time WRITE: In user mode, writing has no effect. 1 = The STOP instruction is converted to HALT instruction 0 = STOP instruction is not converted to HALT instruction (erased state) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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