HC805K3GRSSLASHD datasheet(43/119 Pages) NXP

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General Release Specification

Hardware Interrupts

MC68HC805K3 — Rev. 1.0

Interrupts

4.6 Hardware Interrupts

All hardware interrupts except RESET are maskable by the I bit in the

CCR. If the I bit is set, all hardware interrupts (internal and external) are

disabled. Clearing the I bit enables the hardware interrupts. The two

types of hardware interrupts are explained in the following sections.

4.6.1 External Interrupt (IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block

diagram of the IRQ function is shown in Figure 4-3.

The IRQ pin is one source of an IRQ interrupt, and a mask option register

bit is available to enable the four lower order port A pins (PA0 through

PA3) to act as other IRQ interrupt sources. All of these sources are

combined into a single ORing function that is latched by the IRQ latch.

The IRQ latch is set on the falling edge of the IRQ pin or on the rising

edge of a PA0 through PA3 pin, if port A interrupts have been enabled

by the mask option register bit.

Figure 4-3. IRQ Function Block Diagram

LATCH

VDD

IRQ PIN

IRQE

IRQ SENSITIVITY

MASK OPTION REGISTER BIT

IRQF

TO IRQ

PROCESSING

IN CPU

IRQ VECTOR FETCH

TO BIH & BIL

INSTRUCTION

SENSING

RST

PORT A IRQ

MASK OPTION REGISTER BIT

PA0

PA1

PA2

PA3

IRQR

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 43 Page - NXP Semiconductors

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