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HC805K3GRS/D Datasheet(PDF) 69 Page - NXP Semiconductors |
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HC805K3GRS/D Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 119 page ![]() General Release Specification I/O Port Programming MC68HC805K3 — Rev. 1.0 Parallel Input/Output 69 Table 7-2. PB0 Pin Functions Software Prog. Pulldown Mask Option Register Bit* PDIB0 DDRB0 I/O Pin Mode Access to PDRB at $0011 Access to DDRB at $0005 Access to Data Register at $0001 Read Write Read/Write Read Write 1 X 0 IN, Hi-Z U PDIB0 DDRB0 I/O Pin X 1 X 1 OUT U PDIB0 DDRB0 PB0 PB0 0 0 0 IN, Pulldown U PDIB0 DDRB0 I/O Pin X 0 0 1 OUT U PDIB0 DDRB0 PB0 PB0 0 1 0 IN, Hi-Z U PDIB0 DDRB0 I/O Pin X 0 1 1 OUT U PDIB0 DDRB0 PB0 PB0 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled Table 7-3. PB1/OSC3 Pin Functions Mask Option (3-Pin) Software Prog. Pulldown Mask Option Register Bit* PDIB1 DDRB1 I/O Pin Mode Access to PDRB at $0011 Access to DDRB at $0005 Access to Data Register at $0001 Read Write Read/Write Read Write 0 0 1 0 IN, Hi-Z U PDIB1 DDRB1 I/O Pin X 0 0 1 1 OUT U PDIB1 DDRB1 PB1 PB1 00 0 0 IN, Pulldown U PDIB1 DDRB1 I/O Pin X 0 0 0 1 OUT U PDIB1 DDRB1 PB1 PB1 0 0 0 0 IN, Hi-Z U PDIB1 DDRB1 I/O Pin X 0 0 0 1 OUT U PDIB1 DDRB1 PB1 PB1 1X X X RC OSCOUT U PDIB1 DDRB1 PB1 PB1 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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