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HC805K3GRS/D Datasheet(PDF) 36 Page - NXP Semiconductors |
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HC805K3GRS/D Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 119 page ![]() General Release Specification Registers MC68HC805K3 — Rev. 1.0 36 Central Processing Unit Core 3.3 Registers The MCU contains five registers that are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1. Figure 3-1. M68HC05 Programming Model For a more complete description of the M68HC05 CPU functions, refer to M6805 HMOS, M146805 CMOS Family User’s Manual (M6805UM(AD3), HC05 Applications Guide (M68HC05AG/AD), or Understanding Small Microcontrollers (M68HC05TB/D). Any specific differences in the operation of all CPU registers or bits is described in the following sections. CONDITION CODE REGISTER I 60 A 71 X 4 52 3 STACK POINTER SP 14 8 15 9 12 13 10 11 PC CC 111 11 0 0 0 0 0 0 0 0 HN Z C HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT 1 PROGRAM COUNTER INDEX REGISTER ACCUMULATOR 000000 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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