HC805K3GRSSLASHD datasheet(40/119 Pages) NXP

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General Release Speciﬁcation

CPU Interrupt Processing

MC68HC805K3 — Rev. 1.0

Interrupts

4.3 CPU Interrupt Processing

Interrupts cause the processor to save register contents on the stack

and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike

RESET, hardware interrupts do not cause the current instruction

execution to be halted, but are considered pending until the current

instruction is complete.

If interrupts are not masked (I bit in the CCR is clear) and the

corresponding interrupt enable bit is set, the processor proceeds with

interrupt processing. Otherwise, the next instruction is fetched and

executed. If an interrupt occurs, the processor completes the current

instruction, stacks the current CPU register states, sets the I bit to inhibit

further interrupts, and finally checks the pending hardware interrupts. If

more than one interrupt is pending following the stacking operation, the

interrupt with the highest vector location, shown in Table 4-1, is serviced

first. The SWI is executed the same as any other instruction, regardless

of the I-bit state.

When an interrupt is to be processed, the CPU fetches the address of

the appropriate interrupt software service routine from the vector table at

locations $03F8 through $03FF as defined in Table 4-1.

Table 4-1. Vector Addresses for Interrupts and Reset

Flag Name

Interrupts

CPU

Interrupts

Vector

Addresses

N/A

Reset

RESET

$03FE-$03FF

N/A

Software

SWI

$03FC-$03FD

ISCR

IRQF

External Interrupt

IRQ

$03FA-$03FB

TSCR

TOF

Timer Overﬂow

TIMER

$03F8-$03F9

TSCR

RTIF

Real Time

Interrupt

TIMER

$03F8-$03F9

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 40 Page - NXP Semiconductors

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