HC805K3GRSSLASHD datasheet(51/119 Pages) NXP

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General Release Specification

Resets

MC68HC805K3 — Rev. 1.0

Resets

option register bit selects an oscillator stabilization delay of 16 or 4064

cycles of the internal processor bus clock (PH2).

The POR generates the RST signal that resets the CPU. If any other

reset function is active at the end of this stabilization delay, the RST

signal remains in the reset condition until the other reset condition(s)

end(s).

5.4.2 Computer Operating Properly Reset (COPR)

A COP watchdog timer can be enabled by a mask option register bit. The

internal COP reset (COPR) is generated automatically by a timeout of

the COP watchdog timer. This timeout occurs if the counter in the COP

watchdog timer is not reset (cleared) within a specific time by a user

program reset sequence. Refer to 8.4 COP Watchdog Timer for more

information on this timeout feature.

The COPR generates the RST signal that resets the CPU and other

peripherals. If any other reset function is active at the end of the COPR

reset signal, the RST signal remains in the reset condition until the other

reset condition(s) end(s).

The COP Watchdog reset activates the internal pulldown device

connected to the RESET pin for one cycle of the internal processor bus

clock, PH2.

5.4.3 Illegal Address Reset (ILADR)

The internal ILADR reset is generated when an instruction opcode fetch

occurs from an address in the I/O address area ($0000 through $001F).

The ILADR generates the RST signal that resets the CPU and other

peripherals. If any other reset function is active at the end of the ILADR

reset signal, the RST signal remains in the reset condition until the other

reset condition(s) end(s). The ILADR reset activates the internal

pulldown device connected to the RESET pin for one cycle of the

internal processor bus clock, PH2.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 51 Page - NXP Semiconductors