HC805K3GRSSLASHD datasheet(63/119 Pages) NXP

63 / 119 page

General Release Specification

Port B

MC68HC805K3 — Rev. 1.0

Parallel Input/Output

logic zero level, the other PA0–PA3 IRQ inputs are effectively ignored.

Port interrupts will be generated with the above PA0–PA3 I/O state

regardless of whether the port is configured as an input or output.

NOTE:

The BIH and BIL instructions apply only to the level on the IRQ pin itself,

and not to the internal IRQ input to the CPU. Therefore, BIH and BIL

cannot be used to test the state of the lower four port A input pins as a

group. Each port A interrupt pin can be tested by reading the port A data

7.4 Port B

Port B is a 2-bit bidirectional port that shares one of its pins with the RC

oscillator as shown in Figure 7-3. Each port B pin is controlled by the

corresponding bits in a data direction register, a data register, and a

pulldown register.

The port B data register is located at address $0001. The port B data

direction register (DDRB) is located at address $0005, and the port B

pulldown register (PDRB) is located at address $0011. Reset clears both

the DDRB and the PDRB. The port B data register is unaffected by reset.

7.4.1 Port B Data Register

Each port B I/O pin has a corresponding bit in the port B data register.

When a port B pin is programmed as an output, the state of the

corresponding data register bit determines the state of the output pin.

When a port B pin is programmed as an input, any read of the port B data

to the port B data register is saved in the data register, but not applied to

the corresponding I/O pin. Unused bits 2 through 7 are always read as

logic zeros, and any write to these bits is ignored. The port B data

after initial power-up.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 63 Page - NXP Semiconductors