HC805K3GRSSLASHD datasheet(67/119 Pages) NXP

67 / 119 page

General Release Specification

I/O Port Programming

MC68HC805K3 — Rev. 1.0

Parallel Input/Output

7.5.2 Output Pin

When an I/O pin is programmed as an output pin, the state of the

corresponding data register bit determines the state of the pin. The state

of the data register bits can be altered by writing to address $0000 for

port A and address $0001 for port B. Reads of the corresponding data

is possible on all pins programmed as outputs.

All pins programmed as outputs have their pulldown devices disabled

regardless of the selected mask option register bit for software

programmable pulldowns or the state of their PDR bits.

7.5.3 Input Pin

When an I/O pin is programmed as an input pin, the state of the pin can

be determined by reading the corresponding data register bit. Any writes

to the corresponding data register bit for an input pin is saved by the

later programmed to be an output.

If the corresponding bit in the pulldown register is clear (and the mask

option register bit for software programmable pulldowns is selected), the

input pin also has an activated pulldown device.

Read-modify-write instructions, such as bit manipulation, should not be

used on the pulldown registers, since they are write-only.

7.5.4 I/O Pin Transitions

A “glitch” can be generated on an I/O pin when changing it from an input

to an output unless the data register is first pre-conditioned to the

desired state before changing the corresponding DDR bit from a zero to

a one.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 67 Page - NXP Semiconductors