HC805K3GRSSLASHD datasheet(72/119 Pages) NXP

72 / 119 page

General Release Speciﬁcation

8.6 Operating During Wait Mode

MC68HC805K3 — Rev. 1.0

8-Bit Timer

at location $08. The clock frequency that drives the RTI circuit is fOP/2

(or fOP/16384) with three additional divider stages giving a maximum

interrupt period of fOP/2

17 (or f

OP/131072).

The power-on cycle clears the entire counter chain and begins clocking

the counter. After 4064 or 16 cycles (depending on mask option register

bit), the power-on reset circuit is released, which again clears the

counter chain and allows the device to come out of reset. At this point, if

RESET is not asserted, the timer starts counting up from zero and

normal device operation begins. If RESET is asserted at any time during

operation, the counter chain is cleared.

Figure 8-1. Timer Block Diagram

COPR

CLEAR

MC68HC05 INTERNAL BUS

$09 TCNTR

7-BIT COUNTER

INTERRUPT CIRCUIT

$08 TSCR

RTI SELECT CIRCUIT

OVERFLOW

CIRCUIT

DETECT

COP WATCHDOG

TIMER

TO RESET

LOGIC

TO INTERRUPT

LOGIC

fOP/2

POR

TCBP

TSCR

TCNTR

NTF1 INTERNAL

TIMER CLOCK

(fOP)

TOF

RTIF

TOFE

RTIE

RT1

RT0

RTIFR

TOFR

TIMER STATUS/CONTROL REGISTER

TIMER COUNTER REGISTER (TCNTR)

÷4

÷8

RESET

MOR1,2

REFRESH

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 72 Page - NXP Semiconductors

HC805K3GRS/D Datasheet(HTML) 72 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL