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HC805K3GRS/D Datasheet(PDF) 87 Page - NXP Semiconductors |
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HC805K3GRS/D Datasheet(HTML) 87 Page - NXP Semiconductors |
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87 / 119 page  General Release Specification PEEPROM Read Access MC68HC805K3 — Rev. 1.0 Personality EEPROM 87 Reading the PEEPROM is easiest when each row in the PEEPROM array is mapped to contain one byte of data. Selecting a column zero bit selects the first bit in the row; and incrementing the PEEPROM bit select register (PEBSR) selects the next (column 1) bit from the same row. Incrementing the PEBSR seven more times selects the remaining bits of the row and carries over to select column zero of the next row, thereby setting the column zero flag, PEPCZF in the PESCR. The number of increments per row can be controlled by looping on a test of the PEPCZF flag bit. The complete array can be easily accessed by starting with $7F for the PEBSR and decrementing the PEBSR after each access of the PEDATA bit. The decrement sequence can end when the contents of the PEBSR are zero. NOTE: One byte of data from the PEEPROM can be re-created in the PEBSR itself. This can be done if the read routine builds the 8-bit data byte in the index register or the accumulator and then transfers that result to the PEBSR when completed. Subsequent reads of the PEBSR quickly yield that retrieved data byte. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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