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HC805K3GRS/D Datasheet(PDF) 62 Page - NXP Semiconductors |
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HC805K3GRS/D Datasheet(HTML) 62 Page - NXP Semiconductors |
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62 / 119 page ![]() General Release Specification Port A MC68HC805K3 — Rev. 1.0 62 Parallel Input/Output The PDRA is a write-only register and any reads of location $0010 return undefined results. Since reset clears both the DDRA and the PDRA, all pins initialize as inputs with the pulldown devices active (if enabled by mask option register bit). 7.3.4 Port A LED Drive Capability The outputs of port A pins 4 through 7 are capable of sinking high current for LED drive capability. 7.3.5 Port A I/O Pin Interrupts The inputs for the lower four bits of port A can be connected through an OR gate to the IRQ latched input to the CPU by a mask option register bit. When connected as an alternate source of an IRQ interrupt, the port A input pins behave the same as the IRQ pin itself, except that their active state is a logical one or a rising edge. The normal IRQ pin has an active state that is a logical zero or a falling edge depending on the mask option register bit. If the mask option register bit for edge- and level-sensitive interrupts and the mask option register bit for port A interrupts are both used, the presence of a logic one on any one of the lower four port A pins causes an IRQ interrupt request. If the mask option register bit for edge- sensitive-only interrupts and the mask option register bit for port A interrupts are both used, the occurrence of a rising edge on any one of the PA0–PA3 pins causes an IRQ interrupt request, as long as the other PA0–PA3 pins are at a low level. As long as any one of the PA0 through PA3 IRQ inputs remains at a logic one level, or the IRQ remains at a $0010 Bit 7 65432 1 Bit 0 Read: Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 Reset: 0 00000 0 0 = Unimplemented Figure 7-2. Port A Pulldown Inhibit Register (PDRA) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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