PIC12C67X datasheet(53/129 Pages) MICROCHIP

53 / 129 page

DS30561B-page 53

PIC12C67X

9.0

SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits to deal with the needs of real-

time applications. The PIC12C67X family has a host of

such features intended to maximize system reliability,

minimize cost through elimination of external compo-

nents, provide power saving operating modes and offer

code protection. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

The PIC12C67X has a Watchdog Timer, which can be

shut off only through configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

fixed delay of 72 ms (nominal) on power-up only,

designed to keep the part in reset while the power sup-

ply stabilizes. With these two timers on-chip, most

applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through external reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The INTRC/EXTRC oscillator option saves system

cost, while the LP crystal option saves power. A set of

configuration bits are used to select various options.

9.1

Configuration Bits

The configuration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in pro-

gram memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special test/configuration memory space (2000h-

3FFFh),

which

can

accessed

only

during

programming.

CONFIGURATION WORD

CP1

CP0

CP1

CP0

CP1

CP0 MCLRE

CP1

CP0

PWRTE WDTE FOSC2 FOSC1 FOSC0

CONFIG

Address

2007h

bit13

bit0

bit 13-8, CP<1:0>: Code Protection bit pairs(1)

6-5:

= Code protection off

= Locations 400h through 7FEh code protected (do not use for PIC12C671 and PIC12CE673)

= Locations 200h through 7FEh code protected

= All memory is code protected

bit 7:

MCLRE: Master Clear Reset Enable bit

1 = Master Clear Enabled

0 = Master Clear Disabled

bit 4:

PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3:

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0:

FOSC<2:0>: Oscillator Selection bits

111

= EXTRC, Clockout on OSC2

110

= EXTRC, OSC2 is I/O

101

= INTRC, Clockout on OSC2

100

= INTRC, OSC2 is I/O

011

= Invalid Selection

010

= HS Oscillator

001

= XT Oscillator

000

= LP Oscillator

Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.

PIC12C67X Datasheet(PDF) 53 Page - Microchip Technology

PIC12C67X Datasheet(HTML) 53 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL