PIC12C67X datasheet(78/129 Pages) MICROCHIP

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PIC12C67X

DS30561B-page 78

NOP

No Operation

Syntax:

[

label ]

NOP

Operands:

None

Operation:

No operation

Status Affected:

None

Encoding:

0000

0xx0

0000

Description:

No operation.

Words:

Cycles:

Example

NOP

OPTION

Load Option Register

Syntax:

[

label ]

OPTION

Operands:

None

Operation:

(W)

→ OPTION

Status Affected:

None

Encoding:

0000

0110

0010

Description:

The contents of the W register are

loaded in the OPTION register.

This instruction is supported for

code compatibility with PIC16C5X

products. Since OPTION is a read-

able/writable register, the user can

directly address it.

Words:

Cycles:

Example

To maintain upward compatibility

with future PIC12C67X products,

do not use this instruction.

RETFIE

Return from Interrupt

Syntax:

[

label ]

RETFIE

Operands:

None

Operation:

TOS

→ PC,

→ GIE

Status Affected:

None

Encoding:

0000

1001

Description:

Return from Interrupt. Stack is

POPed and Top of Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global Inter-

rupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words:

Cycles:

Example

RETFIE

After Interrupt

PC =

TOS

GIE =

RETLW

Return with Literal in W

Syntax:

[

label ]

RETLW k

Operands:

≤ k ≤ 255

Operation:

→ (W);

TOS

→ PC

Status Affected:

None

Encoding:

01xx

kkkk

Description:

The W register is loaded with the

eight bit literal ’k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two cycle instruction.

Words:

Cycles:

Example

TABLE

CALL TABLE;W contains

table

;offset value

•

;W now has table value

•

ADDWF PC

;W = offset

RETLW k1

;Begin table

RETLW k2

;

•

RETLW kn

; End of table

Before Instruction

0x07

After Instruction

value of k8

PIC12C67X Datasheet(PDF) 78 Page - Microchip Technology

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