PIC12C67X datasheet(10/129 Pages) MICROCHIP

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PIC12C67X

DS30561B-page 10

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

OSC1

OSC2/CLKOUT

(EXTRC and

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

INTRC modes)

All instructions are single cycle, except for any program branches. These take two cycles since the fetched

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF GPIO

Fetch 2

Execute 2

3. CALL

SUB_1

Fetch 3

Execute 3

4. BSF

GPIO, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1

Execute SUB_1

3.1

Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, and the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

is shown in Figure 3-2.

3.2

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute

are pipelined such that fetch takes one instruction

cycle, while decode and execute takes another

instruction cycle. However, due to the pipelining, each

instruction effectively executes in one cycle. If an

instruction causes the program counter to change

(i.e., GOTO), then two cycles are required to complete

the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the “Instruction Register" (IR) in cycle

Q1. This instruction is then decoded and executed

during the Q2, Q3, and Q4 cycles. Data memory is

read during Q2 (operand read) and written during Q4

(destination write).

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