PIC12C67X datasheet(17/129 Pages) MICROCHIP

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DS30561B-page 17

PIC12C67X

4.2.2.3

INTCON REGISTER

The INTCON Register is a readable and writable regis-

ter, which contains various enable and flag bits for the

TMR0 Register overflow, GPIO port change and exter-

nal GP2/INT pin interrupts.

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

GIE: Global Interrupt Enable bit

= Enables all un-masked interrupts

= Disables all interrupts

bit 6:

PEIE: Peripheral Interrupt Enable bit

= Enables all un-masked peripheral interrupts

= Disables all peripheral interrupts

bit 5:

T0IE: TMR0 Overflow Interrupt Enable bit

= Enables the TMR0 interrupt

= Disables the TMR0 interrupt

bit 4:

INTE: INT External Interrupt Enable bit

= Enables the external interrupt on GP2/INT/T0CKI/AN2 pin

= Disables the external interrupt on GP2/INT/T0CKI/AN2 pin

bit 3:

GPIE: GPIO Interrupt on Change Enable bit

= Enables the GPIO Interrupt on Change

= Disables the GPIO Interrupt on Change

bit 2:

T0IF: TMR0 Overflow Interrupt Flag bit

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 1:

INTF: INT External Interrupt Flag bit

= The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)

= The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur

bit 0:

GPIF: GPIO Interrupt on Change Flag bit

= GP0, GP1 or GP3 pins changed state (must be cleared in software)

= Neither GP0, GP1 nor GP3 pins have changed state

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