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PIC12C67X Datasheet(PDF) 19 Page - Microchip Technology |
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PIC12C67X Datasheet(HTML) 19 Page - Microchip Technology |
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19 / 129 page  © 1999 Microchip Technology Inc. DS30561B-page 19 PIC12C67X 4.2.2.5 PIR1 REGISTER This register contains the individual flag bits for the Peripheral interrupts. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 4-5: PIR1 REGISTER (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 —ADIF — — — — — — R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit7 bit0 bit 7: Unimplemented: Read as ’0’ bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5-0: Unimplemented: Read as ’0’ |
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