PIC12C67X datasheet(64/129 Pages) MICROCHIP

64 / 129 page

PIC12C67X

DS30561B-page 64

9.5.1

TMR0 INTERRUPT

An overflow (FFh

→ 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>)

(Section 7.0).

The

flag

bit

T0IF

(INTCON<2>) will be set, regardless of the state of the

enable bits. If used, this flag must be cleared in software.

9.5.2

INT INTERRUPT

External interrupt on GP2/INT pin is edge triggered;

either rising if bit INTEDG (OPTION<6>) is set, or fall-

ing, if the INTEDG bit is clear. When a valid edge

appears

the

GP2/INT

pin,

flag

bit

INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can wake-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP. The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 9.8 for details on SLEEP mode.

9.5.3

GPIO INTCON CHANGE

An input change on GP3, GP1 or GP0 sets flag bit GPIF

(INTCON<0>). The interrupt can be enabled/disabled by

setting/clearing

enable

bit

GPIE

(INTCON<3>)

(Section 5.1) . This flag bit GPIF (INTCON<0>) will be

set, regardless of the state of the enable bits. If used, this

flag must be cleared in software.

9.6

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt (i.e., W register and STATUS

Example 9-1 shows the storing and restoring of the

STATUS and W registers. The register, W_TEMP, must

be defined in both banks and must be defined at the

same offset from the bank base address (i.e., if

W_TEMP is defined at 0x20 in bank 0, it must also be

defined at 0xA0 in bank 1).

Example 9-2 shows the saving and restoring of STA-

TUS and W using RAM locations 0x70 - 0x7F.

W_TEMP is defined at 0x70 and STATUS_TEMP is

defined at 0x71.

The example:

Stores the W register.

Stores the STATUS register in bank 0.

Executes the ISR code.

Restores the STATUS register (and bank select

bit).

Restores the W register.

Returns from interrupt.

EXAMPLE 9-1:

SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM

(0x20 - 0x6F)

MOVWF

W_TEMP

;Copy W to TEMP register, could be bank one or zero

SWAPF

STATUS,W

;Swap status to be saved into W

BCF

STATUS,RP0

;Change to bank zero, regardless of current bank

MOVWF

STATUS_TEMP

;Save status to bank zero STATUS_TEMP register

:(ISR)

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF

STATUS

;Move W into STATUS register

SWAPF

W_TEMP,F

;Swap W_TEMP

SWAPF

W_TEMP,W

;Swap W_TEMP into W

RETFIE

;Return from interrupt

EXAMPLE 9-2:

SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)

MOVWF

W_TEMP

;Copy W to TEMP register (bank independent)

MOVF

STATUS,W

;Move STATUS register into W

MOVWF

STATUS_TEMP

;Save contents of STATUS register

:(ISR)

MOVF

STATUS_TEMP,W

;Retrieve copy of STATUS register

MOVWF

STATUS

;Restore pre-isr STATUS register contents

SWAPF

W_TEMP,F

;

SWAPF

W_TEMP,W

;Restore pre-isr W register contents

RETFIE

;Return from interrupt

PIC12C67X Datasheet(PDF) 64 Page - Microchip Technology

PIC12C67X Datasheet(HTML) 64 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL