PIC12C67X datasheet(62/129 Pages) MICROCHIP

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PIC12C67X

DS30561B-page 62

9.5

Interrupts

There are four sources of interrupt:

The Interrupt Control Register (INTCON) records indi-

vidual interrupt requests in flag bits. It also has individ-

ual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>),

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt flag bits are set,

regardless of the status of their corresponding mask bit

or the GIE bit. The GIE bit is cleared on reset.

Interrupt Sources

TMR0 Overflow Interrupt

External Interrupt GP2/INT pin

GPIO Port Change Interrupts (pins GP0, GP1, GP3)

A/D Interrupt

Note:

Individual interrupt flag bits are set, regard-

less of the status of their corresponding

mask bit or the GIE bit.

The “return-from-interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

The GP2/INT, GPIO port change interrupt and the

TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag ADIF, is contained in the

Special Function Register PIR1. The corresponding

interrupt enable bit is contained in Special Function

contained in Special Function Register INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the interrupt service routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid repeated interrupts.

For external interrupt events, such as GPIO change

interrupt, the interrupt latency will be three or four

instruction cycles. The exact latency depends on when

the interrupt event occurs (Figure 9-14). The latency is

the same for one or two cycle instructions. Individual

interrupt flag bits are set, regardless of the status of

their corresponding mask bit or the GIE bit.

FIGURE 9-13: INTERRUPT LOGIC

GPIF

GPIE

T0IF

T0IE

GIE

Wake-up

(If in SLEEP mode)

Interrupt to CPU

PEIE

ADIF

ADIE

INTF

INTE

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