7643 datasheet(40/424 Pages) RENESAS

40 / 424 page

Rev.2.00

Aug 28, 2006

page 23 of 103

7643 Group

REJ09B0133-0200

OVERVIEW

Fig. 17 Structure of interrupt-related registers

Interrupt request register A (address 000216)

IREQA

USB function interrupt request bit

Reserved bit (Undefined at read, “0” at write)

INT0 interrupt request bit

INT1 interrupt request bit

DMAC0 interrupt request bit

DMAC1 interrupt request bit

UART receive buffer full interrupt request bit

UART transmit interrupt request bit

Interrupt polarity select register (address 001116)

IPOL

INT0 interrupt edge select bit

INT1 interrupt edge select bit

Reserved bits (“0” at read/write)

0 : Falling edge active

1 : Rising edge active

0 : Interrupts disabled

1 : Interrupts enabled

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt request register B address (address 000316)

IREQB

UART summing error interrupt request bit

Reserved bit (Undefined at read, “0” at write)

Timer 1 interrupt request bit

Timer 2 interrupt request bit

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt control register A (address 000516)

ICONA

USB function interrupt enable bit

Reserved bit (“0” at read/write)

INT0 interrupt enable bit

INT1 interrupt enable bit

DMAC0 interrupt enable bit

DMAC1 interrupt enable bit

UART receive buffer full interrupt enable bit

UART transmit interrupt enable bit

Interrupt request register C (address 000416)

IREQC

Timer 3 interrupt request bit

Reserved bit (Undefined at read, “0” at write)

Serial I/O interrupt request bit

Reserved bit (Undefined at read, “0” at write)

Key input interrupt request bit

Reserved bit (“0” at read/write)

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt control register B (address 000616)

ICONB

UART summing error interrupt enable bit

Reserved bit (“0” at read/write)

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

0 : Interrupts disabled

1 : Interrupts enabled

Interrupt control register C (address 000716)

ICONC

Timer 3 interrupt enable bit

Reserved bit (“0” at read/write)

Serial I/O interrupt enable bit

Reserved bit (“0” at read/write)

Key input interrupt enable bit

Reserved bit (“0” at read/write)

0 : Interrupts disabled

1 : Interrupts enabled

00 00 00

FUNCTIONAL DESCRIPTION

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