7643 datasheet(8/424 Pages) RENESAS

8 / 424 page

Rev.2.00

Aug 28, 2006

page 4 of 12

7643 Group

REJ09B0133-0200

List of figures

CHAPTER 1 HARDWARE

Fig. 1 M37643M8-XXXFP, M37643F8FP pin configuration ....................................................... 3

Fig. 2 M37643M8-XXXHP, M37643F8HP pin configuration ....................................................... 3

Fig. 3 Functional block diagram .................................................................................................... 4

Fig. 4 Part numbering ..................................................................................................................... 7

Fig. 5 Memory expansion ............................................................................................................... 8

Fig. 6 7600 series CPU register structure ................................................................................... 9

Fig. 7 Register push and pop at interrupt generation and subroutine call ........................... 10

Fig. 8 Structure of CPU mode register ...................................................................................... 12

Fig. 9 Memory map diagram ........................................................................................................ 13

Fig. 10 Memory map of special function register (SFR) ......................................................... 14

Fig. 11 Structure of port control and port P2 pull-up control registers ................................. 15

Fig. 12 Port block diagram (1) .................................................................................................... 17

Fig. 13 Port block diagram (2) .................................................................................................... 18

Fig. 14 Port block diagram (3) .................................................................................................... 19

Fig. 15 Port block diagram (4) .................................................................................................... 20

Fig. 16 Interrupt control ................................................................................................................ 21

Fig. 17 Structure of interrupt-related registers .......................................................................... 23

Fig. 18 Connection example when using key input interrupt and port P2 block diagram .. 24

Fig. 19 Timer block diagram ........................................................................................................ 25

Fig. 20 Structure of timer 123 mode register ............................................................................ 26

Fig. 21 Structure of serial I/O control registers 1, 2 ................................................................ 27

Fig. 22 Block diagram of serial I/O ............................................................................................ 28

Fig. 23 Serial I/O timing ............................................................................................................... 29

Fig. 24 UART block diagram ....................................................................................................... 31

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Fig. 25 UART transmit timing (CTS function enabled) ............................................................ 32

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Fig. 26 UART transmit timing (CTS function disbled) .............................................................. 33

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Fig. 27 UART receiving timing (RTS function enabled) ........................................................... 33

Fig. 28 Structure of UART related registers .............................................................................. 36

Fig. 29 DMACx (x = 0, 1) block diagram .................................................................................. 37

Fig. 30 Structure of DMACx related register ........................................................................... 38

Fig. 31 Timing chart for cycle steal transfer caused by hardware-related transfer request ... 40

Fig. 32 Timing chart for cycle steal transfer caused by software trigger transfer request ..... 40

Fig. 33 Timing chart for burst transfer caused by hardware-related transfer request ........ 41

Fig. 34 USB FCU (USB Function Control Unit) block ............................................................. 42

Fig. 35 Structure of USB control register .................................................................................. 46

Fig. 36 Structure of USB address register ................................................................................ 47

Fig. 37 Structure of USB power management register ............................................................ 47

Fig. 38 Structure of USB interrupt status register 1 ............................................................... 48

Fig. 39 Structure of USB interrupt status register 2 ............................................................... 49

Fig. 40 Structure of USB interrupt enable register 1 ............................................................. 49

Fig. 41 Structure of USB interrupt enable register 2 ............................................................. 50

Fig. 42 Structure of USB frame number registers .................................................................... 50

Fig. 43 Structure of USB endpoint 0 IN control register ......................................................... 51

Fig. 44 Structure of USB endpoint x (x = 1, 2) IN control register ....................................... 52

Fig. 45 Structure of USB endpoint x (x = 1, 2) OUT control register ................................... 53

List of figures

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